sadegh saei

B.Sc. electronics GPA 13 from 20 in iran, islamic university of najafabad M.Sc. Computer Engineering GPA 2,8 from 5, gotfried leibniz university of hanover germany, MAster thesis: implementation of an computer vision algorithm on MPSOC FPGA 3 Years of practical experience in Hardware and frameware design for AVR, FPGA

Living in : Germany

Gender : MaleRace : Middle Eastern

0Followers 0Following

Academic Profile

Posts

Contact Information

-Email

sadeghsaeiApplyChance Link

Educations

Computer EngineeringMaster'sUniversität Hannover2023-01-09 Germany

Supervisor's name :M.Sc. Till Fiedler

Title :

Optimization and implementation of an computer vision algorithmus on FPGA Zynq MPSOC

Electronics EngineeringBachelor'sIslamic Azad University Najafabad2014-07-30 Iran

Supervisor's name :Dr. Zanjani

Title :

AVR Evaluation Board

Work Experiences

hardware developer

at durag gmbh

I am currently working in this role

working student hardware

at Continental AG

Start : 31-Dec-2018

End : 31-Dec-2020

English Scores

IELTS30-Apr-2023

5/9Total

Reading :

7/9

Speaking :

5/9

Listening :

5/9

Writing :

4/9

Research Keywords

python

FPGA

computer vision

hardware developer