Mohammad Tabarsi Sochelmaeicover image
Mohammad Tabarsi Sochelmaeiavatar

Mohammad Tabarsi Sochelmaei

Graduate alumnus in Semiconductor Devices, seeking a Ph.D. position to pursue my education, contribute my skills and knowledge for research and synchronize with state-of-the-art lab facilities and research centers. Interested in "modeling, analysis, and design of Junctionless and TFET Transistors ", " simulation and investigation of biosensor transistors", "implementation of logic gates", "conducting research on 2-dimensional materials such as Graphene as RTD and Transistors".
Living in : Iran
Gender : MaleRace : Middle Eastern
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Contact Information

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Mohammad Tab SchSkype ID
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MohammadTabarsiSochelmaeiApplyChance Link

Educations

Shahid Beheshti University logo
Electronics EngineeringMaster'sShahid Beheshti University2017-01-23 Iran
Supervisor's name :Assistant Professor. Arash Yazdanpanah Goharrizi
Title :
Simulation and Performance Analysis of Ultrashort Channel MultiGate Junction less Field-Effect Transistor
Hakim Sabzevari University (Tarbiat Moallem University Sabzevar) logo
Electrical EngineeringBachelor'sHakim Sabzevari University (Tarbiat Moallem University Sabzevar)2014-09-09 Iran
Supervisor's name :Associate Professor. Mohammad Hadi Shahrokh Abadi
Title :
Designing SC Fuse Circuit with ATMEGA 8 or PIC

Work Experiences

Teaching Assistant
at HakimSabzevari University
Start : 31-Dec-2011
End : 31-Mar-2012
Teaching Assistant
at ShahidBeheshti University
Start : 31-Dec-2015
End : 31-May-2016
Teaching Assistant
at ShahidBeheshti University
Start : 31-Dec-2018
End : 31-May-2019
Secretary
at Ground force Army
Start : 20-Apr-2018
End : 15-Dec-2019

English Scores

GRE General18-Mar-2022
316/340Total
Verbal Reasoning :
152/170
Quantitative Reasoning :
164/170
Analytical Writing :
3.5/6
TOEFL26-Nov-2022
92/120Total
Reading :
26/30
Listening :
23/30
Speaking :
19/30
Writing :
24/30
TOEFL01-Jan-0001
107/120Total
Reading :
0/30
Listening :
0/30
Speaking :
0/30
Writing :
0/30

Conferences

Your Presentation Title :
Optimization of Novel L-shaped Gate All Around Junctionless Field Effect Transistor
Conference Name :ICEE
Iran
2022
Your Presentation Title :
Logic Gate Implementation Using UTB-SOI Junction-Less Triple Gate MOSFETS with Dual Material Gate8
Conference Name :ecm.icnf.ir
Iran
2018
Your Presentation Title :
Electrical Characteristics of a Novel Junction-Less Dual Material Cylindrical Double Surrounding Gate MOSFET (JL-DM-CDSG)
Conference Name :www.ieeec.ir
Iran
2017

Research Keywords

Graphene
biosensors
Nanotubes
Silicene
Logic Gates
FinFETs
TFET
Nanoribbons
Device Modeling
Antidotes
CMOS
RTDs
Junctionless Nanowire Transistors

References

Arash Yazdanpanah Goharrizi
ar_yazdanpanah@sbu.ac.ir
Kambiz Abedi
k_abedi@sbu.ac.ir
Ahmad Hajipour
a.hajipour@hsu.ac.ir